1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices. More particularly, the present invention relates to a semiconductor integrated circuit device that includes an output circuit formed of a plurality of MOS transistors.
2. Description of the Background Art
Many driving circuits of portable devices with a battery as the power and switching circuits of switching power supply employ a MOS type transistor (referred to as "MOS transistor" hereinafter) as shown in the circuit diagram of FIG. 2 for the output transistor where a great current flows in order to reduce the power consumption of the semiconductor integrated circuit device to increase the operable time period of the device as much as possible. A MOS transistor operates under voltage control, so that it is not necessary to conduct a base current as in a bipolar transistor. This means that the operating time of the device can be increased by a time period corresponding to the power consumed as a base current. In an output transistor that drives a great current, the loss due to the base current is often too great to be neglected.
The output circuit shown in FIG. 2 includes N type MOS transistors T1 and T2 connected in series between a first power supply voltage (VDD1) and a reference potential (GND), and a P type MOS transistor T3 and an N type MOS transistor T4 having their drains connected to the gate of MOS transistor T1 via an interconnection S1. MOS transistor T3 has its source connected to a second power supply voltage VDD2 that is higher than the first power supply voltage VDD1. MOS transistor T4 has its source connected to GND. A control signal from another circuit not shown is applied to the gates of MOS transistors T3, T4 and T2. The node of MOS transistors T1 and T2 is connected to an output terminal OUT. The N type semiconductor substrate of MOS transistor T3 is connected to the second power supply voltage VDD2. The P type wells of MOS transistors T2 and T4 are connected to GND. The P type well of MOS transistor T1 is connected to a potential identical to that of output terminal OUT.
Resistances R1-R4 of respective MOS transistors indicate the ON resistance when each MOS transistor is conducting (ON). Resistance R5 indicates the resistance of the gate of MOS transistor T1. The resistance of the gates of the MOS transistors other than MOS transistor T1 has a relatively small driving capability, and is not illustrated since the effect by the gate resistance is small.
FIG. 3 shows a layout arrangement of the structure of MOS transistor T1 included in the output circuit of FIG. 2. Referring to FIG. 3, MOS transistor T1' includes a diffusion region that becomes a source region la and a drain region 1b formed by having N type impurities introduced into the semiconductor substrate. A gate 2 formed of a plurality of parallel lines of polysilicon and the like is provided above the region between source region 1a and drain region 1b. The plurality of source regions 1a and drain regions 1b are respectively connected by metal interconnection layers 3a and 3b such as of aluminum to function as one source electrode and one drain electrode. The plurality of source and drain regions la and 1b are also connected to another circuit and another output terminal. Each diffusion region and each metal interconnection layer are electrically connected by a connection hole (contact) 4. The fabrication process thereof corresponds to the general process of forming a MOS. Therefore, details of the fabrication method will not be provided here.
FIG. 3 shows the arrangement in which the driving capability is increased with a conventional MOS transistor. More specifically, a plurality of MOS transistors having a unitary channel width W' several ten to several hundred times the channel length L are connected in parallel to form one MOS transistor T1'. Problems encountered in this conventional arrangement are set forth in the following.
Gate 2 formed of polysilicon having a resistance value (resistivity) per unit area generally as much as several tens .OMEGA. is connected by metal interconnection layer 3c outside the diffusion region. Gate 2 located remote from metal interconnection layer 3c having a resistivity lower than that of polysilicon will have signal transfer delayed due to the resistance of a distributed constant and the parasitic capacitance together with the effect of ON resistances R3 and R4 of MOS transistors T3 and T4. Therefore, the switching rate of conduction and cutoff of MOS transistor T1' is delayed. The switching rate could not be increased. A low switching rate causes a through current to be conducted across the power supply lines at the time of switching to result in a great loss. It was difficult to increase the transfer efficiency to improve the operable time of the device.